CCS Standardfunction   DCVTrg [V] (Uab, Uhigh, Ulow)
 

DCVTrg [V] (Uab, Uhigh, Ulow)

MaxSignalAmplitude [V]

TriggerEdge [p/n]

TriggerLevel [V]

TriggerDelay [s]

IntegrationPeriod [s]

TriggerHigh [i/CU pin [INT]/Test Pt[Str]]

TriggerLow [i/CU pin [INT]/Test Pt[Str]]

Timeout [s]

Mode [m/s]

Description of Function

Internally or externally triggered integrating DC voltage measurement. Depending on mode, this function acts as a control function or a measurement function.

Testing Points

Test point + Reference point

Parameters

MaxSignalAmplitude

Largest amplitude occurring on the signal. Can be used to establish the measurement range or to select a suppressor circuit.

TriggerEdge

Specification of which signal edge is to act as trigger (p = positive edge, n = negative edge).

TriggerLevel

Trigger threshold for measurement relative to trigger signal reference (see Example 1 Beispiel1_DCVTrg , Example 2 Beispiel2_DCVTrg and the example for DCITrg Beispiel_DCITrg ).

TriggerDelay

Trigger delay for the measurement (see Example 1 Beispiel1_DCVTrg , Example 2 Beispiel2_DCVTrg and the example for DCITrg Beispiel_DCITrg ).

IntegrationPeriod

Period over which the signal is integrated. With the output stage tests (Uab, Ulow, Uhigh) the integration period with an inductive load should be taken from the diagram for Example 1 Beispiel1_DCVTrg or Example 2 Beispiel2_DCVTrg , and with an ohmic load, from the diagram for the example for DCITrg Beispiel_DCITrg . In the event of superimposed interference signals, it is advisable - wherever possible - to select a multiple of the interference signal period as the integration period.
If the integration period determined is less than the testing instrument's shortest integration period, the testing system may use a sample & hold measurement instead of an integrating measurement.

TriggerHigh

In the case of external triggering, the control unit pin (e.g. 43) or a (user-) defined signal name from the Signals Table (e.g. UB) is entered here. In the case of internal triggering (trigger signal = test signal), ´i´ is entered here.

TriggerLow

Specification of trigger signal reference:
In the case of external triggering, the control unit pin (e.g. 68) or a (user-) defined signal name from the Signals Table (e.g. UB) is entered here. In the case of internal triggering (trigger signal = test signal reference), ´i´ is entered here.

Timeout

If the test read function receives no measured reading input within the period specified for the timeout, the measurement is aborted.
Standard value: 1s

Mode

The Mode indicates whether the function returns a result (m) or whether the testing instrument is simply prepared for the test (s). Mode m can only be used with periodic test signals. In the case of non-periodic test signals, the test signal is applied and the testing instrument prepared (mode s).  The trigger event is subsequently activated and then the test read function RDCVTrg IDH_RDCVTrg invoked.

Example 1

DCVTrg

100,p,40,10E-6,10E-6,i,i,1,m


Diagram:

tID,p

Integration period after triggering by positive edge

tID,n

Integration period after triggering by negative edge

tD,p

Delay period after triggering by positive edge

tD,n

Delay period after triggering by negative edge

UTr,p

Trigger level, positive edge

UTr,n

Trigger level, negative edge

Ulow

Low potential of test signal

Uhigh

High potential of test signal

Uab

Potential of shut-off peak

Uab90,p

Voltage level at 90% of positive edge of a shut-off peak

Uab90,n

Voltage level at 90% of negative edge of a shut-off peak

Figure 6a: Shut-off peak with internal triggering

Trigger level: UTr,p = 0.5(Uab - Ulow) + Ulow
UTr,n = 0.5(Uhigh - Ulow) + Ulow
Uab90,p = 0.9(Uab - Ulow) + Ulow
Uab90,n = 0.9(Uab - Uhigh) + Uhigh

Trigger delay: tD,p = 0.4(t3 - t2) + (t2 - t1)
tD,n = 0.4(t6 - t5) + (t5 - t4)

Integration period: tID,p = 0.2(t3 - t2)
tID,n = 0.2(t6 - t5)


Example 2

DCVTrg

100,p,40,10E-6,10E-6,43,68,1,m



Test circuit:



Diagram:


tID,p

Integration period after triggering by positive edge

tD,p

Delay period after triggering by positive edge

Ulow

Low potential of test signal

Uhigh

High potential of test signal

Uab

Potential of shut-off peak

Uab90,p

Voltage level at 90% of positive edge of a shut-off peak

Uab90,n

Voltage level at 90% of negative edge of a shut-off peak

UTr,p

Trigger level, positive edge

UTr,low

Low potential of trigger signal

UTr,high

High potential of trigger signal

Figure 6b: Shut-off peak with external triggering

With triggering by positive edge of trigger signal, the following applies:

Trigger level: UTr,p = 0.5(UTr,high - UTr,low) + UTr,low

Trigger delay: tD,p = 0.4(t2 - t1) + (t1 - t0)

Integration period: tID,p = 0.2(t2 - t1)

With triggering by negative edge of trigger signal, the following applies:

Trigger level: UTr,n = 0.5(UTr,high - UTr,low) + UTr,low